HPCA-12 Call for Papers 12th International Symposium on High-Performance Computer Architecture Austin, Texas, February 11-15, 2006 http://www.hpcaconf.org/hpca12 The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: * Processor architectures * Cache and memory systems * Parallel computer architectures * Impact of technology on architecture * Power-efficient architectures and techniques * High-availability architectures * High-performance I/O systems * Embedded and reconfigurable architectures * Interconnect and network interface architectures * Network processor architectures * Innovative hardware/software trade-offs * Impact of compilers on architecture * Performance evaluation of real machines Authors should submit an abstract before Monday, July 11, 2005, 9pm PST. They should submit the full version of the paper before Monday, July 18, 2005, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in http://www.hpcaconf.org/hpca12 Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations. Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution. New-idea papers are encouraged. Submission issues should be directed to the program chair at das@cse.psu.edu. Workshop and tutorial submissions should be directed to the workshop and tutorial chair. Important dates * Abstract submission deadline : July 11, 2005, 9pm PST (firm deadline) * Paper submission deadline: July 18, 2005, 9pm PST (firm deadline) * Workshop and tutorial proposals due: August 12, 2005 * Author notification: October 7, 2005 Sponsored by the IEEE Computer Society TC on Computer Architecture General Co-Chairs: Yale Patt, UT Austin Craig Chase, UT Austin Program Chair: Chita R. Das, Penn State Program Committee: Laxmi Bhuyan, UC Riverside Ricardo Bianchini, Rutgers Univ. David Brooks, Harvard Doug Burger, UT Austin Derek Chiou, UT Austin Frederic T. Chong, UC Davis Dan Connors, Colorado Tom Conte, NCSU Srini Devadas, MIT Jose Duato, Univ. Politecnica Valencia Michel Dubois, USC Rajiv Gupta, Arizona James C. Hoe, CMU Ravi Iyer, Intel Mahmut Kandemir, Penn State Eun Jung Kim, Texas A&M Mikko Lipasti, Univ. of Wisconsin Kai Li, Princeton Scott Mahlke, Michigan Randy Moulic, IBM T.J. Watson Trevor Mudge, Michigan Ashwini Nanda, IBM T.J. Watson Vijaykrishnan Narayanan, Penn State Mark Oskin, Washington Dhabaleswar K. (DK) Panda, OSU Sanjay Patel, UIUC Li-Shiuan Peh, Princeton Milos Prvulovic, GATECH Michael Shebanow, NVIDIA Anand Sivasubramaniam, Penn State Per Stenstrom, Chalmers University of Technology Josep Torrellas, UIUC Dean M. Tullsen, UCSD Mateo Valero, Univ. Politecnica Catalunya Pen-Chung Yew, Minnesota Qing Yang, Rhode Island Raj Yavatkar, Intel Mazin Yousif, Intel Yuanyuan Zhou, UIUC Industry Liaison Chair: Mazin Yousif, Intel Local Arrangements Chair: Derek Chiou, UT Austin Workshop and Tutorial Chair: Yan Solihin Publicity and Publications Chair: Ki Hwan Yum, UT San Antonio Finance and Registration Chair: Craig Chase, UT Austin Web Chair: Vijaykrishnan Narayanan, Penn State Steering Committee: Dharma Agrawal, Univ. of Cincinnati Laxmi Bhuyan, Univ. of California, Riverside Jean-Luc Gaudiot, Univ. of California, Irvine Yale Patt, UT Austin Josep Torrellas, UIUC Justin Rattner, Intel